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frequency-multiplying, peak-reducing emi solution CY25245 cypress semiconductor corporation ? 3901 north first street san jose , ca 95134 408-943-2600 document #: 38-07124 rev. *a revised january 7, 2003 features ? cypress premis? smartspread? family offering generates an electromagnetic interference (emi) optimized clocking signal at the output selectable output frequency range single 1.25%, 2.5%, 5%, or 10% down or center spread output integrated loop filter components operates with a 3.3 or 5v supply low power cmos design available in 20-pin small shrunk outline package (ssop) key specifications supply voltages: .......................................v dd = 3.3v 0.3v or v dd = 5v 10% frequency range:............................ 13 mhz f in 166 mhz cycle-to-cycle jitter: ......................................... 250 ps (max) output duty cycle: ................................ 40/60% (worst case) notes: 1. pins marked with ^ are internal pull-down resistors with weak 250 k ?. 2. pins marked with * are internal pull-up resistors with weak 80 k ?. CY25245 20 19 18 17 1 2 3 4 x1 x2 avdd mw0^ refout vdd gnd ir1* 5 6 7 14 15 16 ir2* ssout mw1* sdata or1^ 8 9 10 11 12 13 vdd mw2^ or2* sson#^ gnd gnd simplified block diagram pin configuration ssop spread spectrum CY25245 (emi suppressed) 3.3v or 5.0v oscillator or spread spectrum CY25245 (emi suppressed) 3.3v or 5.0v xtal x1 x2 reference input input output output x1 sclk sdata sdata sclk serial interface serial interface sclk [1, 2]
CY25245 document #: 38-07124 rev. *a page 2 of 11 pin definitions pin name pin no. pin type pin description ssout 15 o output modulated frequency . frequency modulated copy of the input clock (sson# asserted). refout 20 o non-modulated output . this pin provides a copy of the reference frequency. this output will not have the spread spectrum feature enabled regardless of the state of logic input sson#. x1 1 i crystal connection or external reference frequency input . this pin has dual functions. it may either be connected to an external crystal, or to an external reference clock. x2 2 i crystal connection . input connection for an external crystal. if using an external reference, this pin must be left unconnected. sson# 10 i spread spectrum control (active low) . asserting this signal (active low) turns the internal modulation waveform on. this pin has an internal pull-down resistor. mw0:2 4, 11, 14 i modulation width selection . when spread spectrum feature is turned on, these pins are used to select the amount of variation and peak emi reduction that is desired on the output signal. mw0:down, mw1:up, mw2:down (see table 2 ). ir1:2 17, 16 i reference frequency selection . the logic level provided at this input indicates to the internal logic what range the reference frequency is in and determines the factor by which the device multiplies the input frequency. refer to table 3 . these pins have internal pull-up resistors. or1:2 6, 9 i output frequency selection bits . these pins select the frequency operation for the output. refer to table 1 . the or2 pin has an internal pull-up resistor. the or1 pin has an internal pull-down resistors. sclk 7 i clock pin for smbus circuitry . sdata 5 i/o data pin for smbus circuitry . vdd 12, 19 p power connection . connected to 3.3v or 5v power supply. avdd 3 p analog power connection . connected to 3.3v or 5v power supply. gnd 8, 13, 18 g ground connection . connect all ground pins to the common ground plane. table 1. frequency configuration (frequencies in mhz) range of fin frequency multiplier settings output/ input range of fout required r settings modulation and power-down settings min. max. or2 or1 min. max. ir2 ir1 mw2 mw1 14 41.7 0 1 1 14 41.7 0 1 table 2 14 41.7 1 0 2 28 83.3 0 1 table 2 14 41.7 1 1 4 56 166 0 1 table 2 25 83.3 0 1 0.5 13 41.7 1 0 table 2 25 83.3 1 0 1 25 83.3 1 0 table 2 25 83.3 1 1 2 50 166 1 0 table 2 50 166 0 1 0.25 13 41.7 1 1 table 2 50 166 1 0 0.5 25 83.3 1 1 table 2 50 166 1 1 1 50 166 1 1 table 2 reserved 0 0 n/a n/a n/a as set as set 1 0 power-down hi-z 0 0 n/a n/a n/a as set as set 1 1 power-down 0 0 0 n/a n/a n/a as set as set 0 0 power-down 1 0 0 n/a n/a n/a as set as set 0 1
CY25245 document #: 38-07124 rev. *a page 3 of 11 overview the CY25245 product is one of a series of devices in the cypress premis family. the premis family incorporates the latest advances in pll spread spectrum frequency synthe- sizer techniques. by frequency modulating the output with a low-frequency carrier, peak emi is greatly reduced. use of this technology allows systems to pass increasingly difficult emi testing without resorting to costly shielding or redesign. in a system, not only is emi reduced in the various clock lines, but also in all signals which are synchronized to the clock. therefore, the benefits of using this technology increase with the number of address and data lines in the system. the simplified block diagram shows a simple implementation. functional description the CY25245 uses a phase-locked loop (pll) to frequency modulate an input clock. the result is an output clock whose frequency is slowly swept over a narrow band near the input signal. the basic circuit topology is shown in figure 1 . the input reference signal is divided by q and fed to the phase detector. a signal from the vco is divided by p and fed back to the phase detector also. the pll will force the frequency of the vco output signal to change until the divided output signal and the divided reference signal match at the phase detector input. the output frequency is then equal to the ratio of p/q times the reference frequency. [3] the unique feature of the spread spectrum frequency timing generator is that a modulating waveform is superimposed at the input to the vco. this causes the vco output to be slowly swept across a predetermined frequency band. because the modulating frequency is typically 1000 times slower than the fundamental clock, the spread spectrum process has little impact on system performance. frequency selection with ssftg in spread spectrum frequency timing generation, emi reduction depends on the shape, modulation percentage, and frequency of the modulating waveform. while the shape and frequency of the modulating waveform are fixed for a given frequency, the modulation percentage may be varied. using frequency select bits (fs2:1 pins), the frequency range can be set (see table 2 ). spreading percentage is set with pins mw0:2 as shown in table 2 . a larger spreading percentage improves emi reduction. however, large spread percentages may either exceed system maximum frequency ratings or lower the average frequency to a point where performance is affected. for these reasons, spreading percentage options are provided. note: 3. for the CY25245, the output frequency is nominally equal to the input frequency. table 2. modulation width selection table emi reduction modulation setting bandwith limit frequencies as a % value of fout mw0 = 0 mw0 = 1 mw2 mw1 low high low high minimum emi control 0 0 98.75% 100% 99.375% 100.625% suggested setting 0 1 97.5% 100% 98.75% 101.25% alternate setting 1 0 95.0% 100% 97.5% 102.5% maximum emi reduction 1 1 90.0% 100% 95% 105% freq. phase modulating vco post clkout detector charge pump waveform dividers divider feedback divider pll gnd v dd q p clock input reference input (emi suppressed) figure 1. functional block diagram
CY25245 document #: 38-07124 rev. *a page 4 of 11 spread spectrum frequency timing generator the device generates a clock that is frequency modulated in order to increase the bandwidth that it occupies. by increasing the bandwidth of the fundamental and its harmonics, the ampli- tudes of the radiated electromagnetic emissions are reduced. this effect is depicted in figure 2 . as shown in figure 2 , a harmonic of a modulated clock has a much lower amplitude than that of an unmodulated signal. the reduction in amplitude is dependent on the harmonic number and the frequency deviation or spread. the equation for the reduction is db = 6.5 + 9*log 10 (p) + 9*log 10 (f) where p is the percentage of deviation and f is the frequency in mhz where the reduction is measured. the output clock is modulated with a waveform depicted in figure 3 . this waveform, as discussed in ? spread spectrum clock generation for the reduction of radiated emissions ? by bush, fessler, and hardin, produces the maximum reduction in the amplitude of radiated electromagnetic emissions. the deviation selected for this chip is as described in table 2 . figure 3 details the cypress spreading pattern. cypress does offer options with more spread and greater emi reduction. contact your local sales representative for details on these devices. serial data interface the CY25245 features a two-pin, serial data interface that can be used to configure internal register settings that control particular device functions. upon power-up, the CY25245 initializes with default register settings, therefore the use of this serial data interface is optional. the serial interface is write-only (to the clock chip) and is the dedicated function of device pins sdata and sclock. in motherboard applica- tions, sdata and sclock are typically driven by two logic outputs of the chipset. clock device register changes are normally made upon system initialization, if any are required. the interface can also be used during system operation for power management functions. table 3 summarizes the control functions of the serial data interface. operation data is written to the CY25245 in eleven bytes of eight bits each. bytes are written in the order shown in table 4 . spread spectrum enabled emi reduction spread spectrum non- frequency span (mhz) down spread amplitude (db) figure 2. clock harmonic with and without sscg modulation frequency domain representation max. min. 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% 10% 20% 30% 40% 50% 60% 70% 80% 90% 100% frequency figure 3. typical modulation profile
CY25245 document #: 38-07124 rev. *a page 5 of 11 writing data bytes each bit in data bytes 0 ? 7 control a particular device function except for the ? reserved ? bits which must be written as a logic 0. bits are written msb (most significant bit) first, which is bit 7. table 5 gives the bit formats for registers located in data bytes 0 ? 7. table 3. serial data interface control functions summary control function description common application clock output disable any individual clock output(s) can be disabled. disabled outputs are actively held low. unused outputs are disabled to reduce emi and system power. examples are clock outputs to unused pci slots. cpu clock frequency selection provides cpu/pci frequency selections through software. frequency is changed in a smooth and controlled fashion. for alternate microprocessors and power management options. smooth frequency transition allows cpu frequency change under normal system operation. spread spectrum enabling enables or disables spread spectrum clocking. for emi reduction. output three-state puts clock output into a high-impedance state. production pcb testing. (reserved) reserved function for future device revision or production device testing. no user application. register bit must be written as 0. table 4. byte writing sequence byte sequence byte name bit sequence byte description 1 slave address 11010010 commands the CY25245 to accept the bits in data bytes 0 ? 6 for internal register configuration. since other devices may exist on the same common serial data bus, it is necessary to have a specific slave address for each potential receiver. the slave receiver address for the CY25245 is 11010010. register setting will not be made if the slave address is not correct (or is for an alternate slave receiver). 2 command code don ? t care unused by the CY25245, therefore bit values are ignored ( ? don ? t care ? ). this byte must be included in the data write sequence to maintain proper byte allocation. the command code byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. 3 byte count don ? t care unused by the CY25245, therefore bit values are ignored ( ? don ? t care ? ). this byte must be included in the data write sequence to maintain proper byte allocation. the byte count byte is part of the standard serial communication protocol and may be used when writing to another addressed slave receiver on the serial data bus. 4 data byte 0 refer to table 5 the data bits in data bytes 0 ? 7 set internal CY25245 registers that control device operation. the data bits are only accepted when the address byte bit sequence is 11010010, as noted above. for description of bit control functions, refer to table 5 , data byte serial configuration map. 5data byte 1 6data byte 2 7data byte 3 8data byte 4 9data byte 5 10 data byte 6 11 data byte 7
CY25245 document #: 38-07124 rev. *a page 6 of 11 table 5. data bytes 0 ? 7 serial configuration map bit(s) affected pin control function bit control default pin no. pin name 0 1 data byte 0 7 ?? (reserved) ?? 0 6 ?? (reserved) ?? 0 5 ?? (reserved) ?? 0 4 ?? (reserved) ?? 0 3 ?? (reserved) ?? 0 2 ?? (reserved) ?? 0 1 ?? (reserved) ?? 0 0 ?? (reserved) ?? 0 data byte 1 7 ?? (reserved) ?? 0 6 ?? (reserved) ?? 0 5 ?? (reserved) ?? 0 4 ?? (reserved) ?? 0 3 ?? (reserved) ?? 0 2 ?? (reserved) ?? 0 1 ?? (reserved) ?? 0 0 ?? (reserved) ?? 0 data byte 2 7 ?? (reserved) ?? 0 6 ?? (reserved) ?? 0 5 ?? (reserved) ?? 0 4 ?? (reserved) ?? 0 3 ?? (reserved) ?? 0 2 ?? (reserved) ?? 0 1 ?? (reserved) ?? 0 0 ?? (reserved) ?? 0 data byte 3 7 ?? (reserved) ?? 0 6 ?? (reserved) ?? 0 5 ?? (reserved) ?? 0 4 ?? (reserved) ?? 0 3 ?? (reserved) ?? 0 2 ?? (reserved) ?? 0 1 ?? (reserved) ?? 0 0 ?? (reserved) ?? 0 data byte 4 7 16 ir2 msb of input range select refer to table 1 0 6 17 ir1 lsb of input range select refer to table 1 1 5 9 or2 msb of output range select refer to table 1 1 4 6 or1 lsb of output range select refer to table 1 0 3 ?? hardware/software frequency select hardware software 0 2 ?? stop function normal stop 0
CY25245 document #: 38-07124 rev. *a page 7 of 11 1 10 sson# spread spectrum spread on spread off 0 0 4 mw0 lsb of modulation width selection refer to table 2 0 data byte 5 7 11 mw2 msb of modulation width selection refer to table 2 0 6 14 mw1 modulation width selection bit refer to table 2 1 5 20 refout output enable disabled enabled 1 4 15 ssout output enable disabled enabled 1 3 ?? (reserved) ?? 0 2 ?? (reserved) ?? 0 1 ?? (reserved) ?? 0 0 ?? (reserved) ?? 0 data byte 6 7 ?? (reserved) ?? 0 6 ?? (reserved) ?? 0 5 ?? (reserved) ?? 0 4 ?? (reserved) ?? 0 3 ?? (reserved) ?? 0 2 ?? (reserved) ?? 0 1 ?? (reserved) ?? 0 0 ?? (reserved) ?? 0 data byte 7 7 ?? (reserved) ?? 0 6 ?? (reserved) ?? 0 5 ?? (reserved) ?? 0 4 ?? (reserved) ?? 0 3 ?? (reserved) ?? 0 2 ?? (reserved) ?? 0 1 ?? (reserved) ?? 0 0 ?? (reserved) ?? 0 table 5. data bytes 0 ? 7 serial configuration map (continued) bit(s) affected pin control function bit control default pin no. pin name 0 1
CY25245 document #: 38-07124 rev. *a page 8 of 11 absolute maximum ratings stresses greater than those listed in this table may cause permanent damage to the device. these represent a stress rating only. operation of the device at these or any other condi- tions above those specified in the operating sections of this specification is not implied. maximum conditions for extended periods may affect reliability. parameter description rating unit v dd , v in voltage on any pin with respect to gnd ? 0.5 to +7.0 v t stg storage temperature ? 65 to +150 c t a operating temperature 0 to +70 c t b ambient temperature under bias ? 55 to +125 c p d power dissipation 0.5 w dc electrical characteristics : 0 c < t a < 70 c, v dd = 3.3v 0.3v [4] parameter description test condition min. typ. max. unit i dd supply current 18 32 ma t on power up time first locked clock cycle after power good 5ms v il input low voltage 0.8 v v ih input high voltage 2.4 v v ol output low voltage 0.4 v v oh output high voltage 2.4 v i il input low current note 4 ? 50 50 a i ih input high current note 4 ? 50 50 a i ol output low current @ 0.4v, v dd = 3.3v 15 ma i oh output high current @ 2.4v, v dd = 3.3v 15 ma c i input capacitance 7pf r p input pull-up resistor 250 k ? z out clock output impedance 25 ? dc electrical characteristics: 0 c < t a < 70 c, v dd = 5v 10% parameter description test condition min. typ. max. unit i dd supply current 30 50 ma t on power up time first locked clock cycle after power good 5ms v il input low voltage 0.15v dd v v ih input high voltage 0.7v dd v v ol output low voltage 0.4 v v oh output high voltage 2.4 v i il input low current note 4 ? 50 50 a i ih input high current note 4 ? 50 50 a i ol output low current @ 0.4v, v dd = 5v 24 ma i oh output high current @ 2.4v, v dd = 5v 24 ma c i input capacitance 7pf r p input pull-up resistor 250 k ? z out clock output impedance 25 ? note: 4. inputs or1:2 and ir1:2 have a pull-up resistor, input sson# has a pull-down resistor.
CY25245 document #: 38-07124 rev. *a page 9 of 11 layout example ac electrical characteristics: t a = 0 c to +70 c, v dd = 3.3v 0.3v or 5v10% parameter description test condition min. typ. max. unit f in input frequency input clock 14 166 mhz f out output frequency spread off 13 166 mhz t r output rise time 15-pf load, 0.8v ? 2.4v 2 5 ns t f output fall time 15-pf load, 2.4v ? 0.8v 2 5 ns t od output duty cycle 15-pf load 40 60 % t id input duty cycle 40 60 % t jcyc jitter, cycle-to-cycle 250 300 ps ordering information ordering code package type product flow CY25245pvc 20-pin plastic ssop (209-mil) commercial, 0 c to 70 c CY25245pvct 20-pin plastic ssop (209-mil)- tape and reel g fb f 0.005 f g g vddq3 c3 20 19 18 17 16 15 14 13 12 1 2 3 4 5 6 7 8 9 10 11 g = via to gnd plane layer v =via to respective supply plane layer note: each supply plane or strip should have a ferrite bead and capacitors ceramic caps c1 = 10 ? 22 f c2 = 0.005 f fb = vishay ilb1206 ? 300 (300 ? @ 100 mhz) or tdk acb2012l-120 or murata blm21b601 all bypass caps = 0.1 f ceramic. g v g v g v g g g g g g g g CY25245
CY25245 document #: 38-07124 rev. *a page 10 of 11 ? cypress semiconductor corporation, 2003. the information contained herein is subject to change without notice. cypress semico nductor corporation assumes no responsibility for the use of any circuitry other than circuitry embodied in a cypress semiconductor product. nor does it convey or imply any license unde r patent or other rights. cypress semiconductor does not authorize its products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected t o result in significant injury to the user. the inclusion of cypress semiconductor products in life-support systems application implies that the manufacturer assumes all risk of such use and in do ing so indemnifies cypress semiconductor against all charges. package drawing and dimension premis and smartspread are trademarks of cypress semiconductor corporation. all product and company names mentioned in this document are the trademarks of their respective holders. 20-pin (5.3 mm) shrunk small outline package o20 51-85077-*c
CY25245 document #: 38-07124 rev. *a page 11 of 11 document history page document title: CY25245 frequency-multiplying, peak-reducing emi solution document number: 38-07124 rev. ecn no. issue date orig. of change description of change ** 109865 11/13/01 ika new data sheet *a 122550 01/08/03 rgl added smartspread ? in the features area

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